1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having an element region and a wiring region, wherein a data bus formed in the wiring region is driven by a bus driver circuit.
2. Description of the Related Art
FIG. 5 is a block diagram showing a layout of a common microcontroller. The microcontroller includes various function blocks such as CPU 11, ROM 12, RAM 13, timer 14 and I/0 port 15. Data transfer among these function blocks is performed through data bus 16, which comprises signal lines for data transfer. Fou signal lines are used in a 4-bit microcontroller and eight signal lines are used in an 8-bit microcontroller.
FIG. 6 is a circuit diagram showing part of an 8-bit microcontroller having a layout such as shown in FIG. 5 and which includes data bus 16 having eight signal lines D0 to D7, timer 14, and I/0 port 15. FIG. 7 is a timing chart showing an example of data transfer performed using signal line D5 of data bus 16.
When clock signal .phi. is in a period of "1", P-channel MOS transistor 21 connected to signal line D5 is turned on and signal line D5 is precharged. Data on signal line D5 thus becomes "1". If control signal A is "1" when clock signal .phi. is in a period of "1", an output of AND gate 22 in timer 14 is "1" and N-channel MOS transistor 23, supplied with the output of gate 22, is turned on. If data DATA1 timer 14 is "1", N-channel MOS transistor 24 is turned on, so that signal line D5 is discharged as a reference voltage (GND) and data on signal line D5 becomes "0". If control signal B in I/O port 15 is "1" during this period, an output of AND gate 25 becomes "1". Data "0" on signal line D5 is latched by latch circuit 26, which is supplied with the output of gate 25 as a clock signal, and its inverted output data DATA2 becomes "1". (period T1 in FIG. 7)
If control signal B is "0" when clock signal .phi. is "1", control signal A is "1" and data DATA1 is "1", data on signal line D5 is set at "0" by timer 14. Since no clock signal is supplied to latch circuit 26 in I/O port 15, output data DATA2 of latch circuit 26 does not vary. (period T2 in FIG. 7)
If data Data1 in timer 14 is "0" when clock signal .phi. is "1" and control signal A is "1", N-channel MOS transistor 23 is turned off. Since a current path extending from signal line D5 to reference voltage GND is not formed in this case, data "1" of precharged signal line D5 is held dynamically as it is by the parasitic capacitance of signal line D5. If control signal B is "1" during this period, data "1" on signal line D5 is latched by latch circuit 26 and its inverted output data DATA2 becomes "0". (period T3 in FIG. 7)
When data is transferred using a data bus as described above, the transfer of data depends on whether charges previously stored in the parasitic capacitance of the data bus during the precharge period are emitted or not. This method of data transfer has a drawback in that no data can be transferred during the precharge period when charges are stored in the parasitic capacitance of the data bus, but also has the advantage in that since the MOS transistors 23 and 24, which are used as bus drivers for driving the data bus, are both constituted by N-channel MOS transistors, the parasitic capacitance of the data bus is smaller than that of a CMOS type bus driver using both a P-channel and an N-channel MOS transistors, with the result that data can be transferred at high speed.
FIG. 8 is a plan view showing a conventional pattern in which the N-channel MOS transistors 23 and 24 constituting a bus driver in the circuit shown in FIG. 6 are formed on an LSI. The components of FIG. 8 corresponding to those of FIG. 6 are indicated by the same reference numerals. Eight signal lines D0 to D7, constituting data bus 16, are made of metal such as aluminum and formed in wiring region 30 on a chip. Other signal lines 31 adjacent to signal line D7 are formed within wiring region 30. Signal lines 31 are also made of aluminum, as is power supply wire 33 for reference voltage (GND), and which is formed within element region 32 adjacent to signal line 31.
In FIG. 8, reference numerals 34, 35, and 36 denote N-type diffusion layers serving as the source and drain regions of N-channel MOS transistors 23 and 24. Diffusion layer 34 contacts signal line D5 through contact hole 37, and diffusion layer 36 contacts power supply wire 33 through contact hole 38. Polycrystalline silicon wire 39, which serves as a gate electrode of N-channel MOS transistor 23 and is supplied with signal A.multidot..phi. output from AND gate 22, is interposed between diffusion layers 34 and 35. Similarly, polycrystalline silicon wire 40, which serves as a gate electrode of N-channel MOS transistor 24 and is supplied with data Data1, is interposed between diffusion layers 35 and 36.
As described above, in the conventional semiconductor integrated circuit, the power supply wire for GND connected to the bus driver is formed within the element region and is used to constitute a logic circuit. There are many cases where various elements, now shown, are formed between wiring region 30 and power supply wire 33 formed within element region 32. Inevitably, diffusion layer 36 is lengthened and an equivalent resistance in diffusion layer 36 is increased.
The function blocks housed in the LSI perform complicated processings. The larger the constitution of the function blocks, the larger is wiring region 30. Further, since the bit length of data is increased from 4 bit or 8 bit to 16 bit or 32 bit, the wiring region is enlarged.
FIG. 9 is a plan view showing a pattern corresponding to that of FIG. 8, wherein data is 32 bits in length and the number of signal lines of data bus 16 is increased up to 32 (D0 to D31), resulting in wiring region 30 being enlarged. With wiring region 30 enlarged, the length of diffusion layer 36 is greater than in the pattern shown in FIG. 8.
FIG. 10 illustrates an equivalent circuit of the bus driver shown in FIG. 9. Since N type diffusion layer 36 is lengthened in this circuit, resistor R having a high resistance is equivalently inserted between the source of transistor 24 (shown in FIG. 8) and power supply wire 33 for GND in the bus driver. Consequently, the discharge characteristic of signal line D5 is degraded. More specifically, when signal line D5 is discharged, a current flows through two MOS transistors 23 and 24 and resistor R which are connected in series. Then, a voltage drop occurs on resistor R and the potential at the source region of transistor 24 is increased. As a result, transistor 24, which is operated at point a shown in FIG. 11 at the beginning of the flow of current, is operated at point b, since both voltage V.sub.DS between the source and drain regions and voltage V.sub.GS between the gate and the source region are lowered by the increase in the source potential. The current flowing into the bus driver is thus reduced and the time required for discharging signal line D5 is lengthened. The increase in the source potential causes difference V.sub.BS between the source potential and a potential under the channel region of the N-channel MOS transistor to be reduced. Therefore, a strong back gate bias effect is generated by the N-channel MOS transistor, and the current is reduced further, increasing the threshold voltage.
As described above, in the conventional integrated circuit, the bus driver circuit is connected to the power supply wire formed in the element region through long diffusion layer 36 including resistive components, with the result that the discharge characteristic of the bus driver circuit is degraded and thus data cannot be transferred at high speed.